1. Technical Field
The present invention relates to programming a memory device not having a Joint Test Action Group (JTAG) port through a component having a JTAG interface.
2. Related Art
A configuration memory internal to a Programmable Logic Device (PLD) is typically programmed through a PLD's JTAG port. JTAG is a four-wire interface primarily used for system testing and debugging, but the JTAG interface is also commonly used as a programming interface for Field Programmable Gate Arrays (FPGAs), Complex PLDs (CPLDs), and some microcontrollers, processors, and digital signal processors (DSPs.). Two defining specifications for JTAG are IEEE 1149.1 and IEEE 1532.
PLDs are typically used on a Printed Circuit Board (PCB) to enable programming or instantiating various components on the PCB. The first prototype PCB, however, poses a problem—how to load the first code, such as boot up code into an external memory attached to the PLD. The external memory can be preprogrammed before populating the PCB, but that assumes the code is ready in time and will not require changes.
As one answer, some PLD manufacturers make external memory devices for storing the PLD configuration data that include a dedicated JTAG port as a programming interface connection to the PLD. One such manufacturer is Xilinx, Inc. of San Jose, Calif. which provides a Programmable Read Only Memory (PROM) with a JTAG programming port. Most commodity memories such as flash and DDR SDRAM are not typically used as configuration memories for PLDs, and do not have a JTAG interface or a JTAG programming infrastructure, including JTAG programming hardware and associated software to enable programming. With advances in FPGAs and other PLDs, however, commodity memory devices such as byte-wide parallel flash and Serial Peripheral Interface (SPI) flash that do not have a JTAG port may be used to store an FPGA's configuration program.
Another answer to programming an external configuration storage memory that does not have a dedicated JTAG is described with reference to the components of FIG. 1. The method uses the JTAG interface 4 of a component 2, such as a PLD, and a separate non-JTAG communication port 6 to connect and communicate with the attached memory device 8. The method uses the JTAG interface components, including the Boundary Scan Chain (BSC) elements 10 and JTAG port 7 of the component 2 as a serial interface between the JTAG interface 4 and the non-JTAG interface 6; the method avoids programming or instantiating hardware into the component 2. Data is provided serially between the primary Test Data Input (TDI) pin and the primary Test Data Output (TDO) pin of the JTAG access port 7. The Test Access Port (TAP) controls data flow and receives JTAG control signals from the Test Mode Select (TMS) and Test Clock (TCK) inputs. This method of providing a serial interface between a JTAG and non-JTAG port uses the JTAG EXTEST instruction and sometimes the SAMPLE/PRELOAD instruction to control the boundary scan chain, and is therefore referred to herein as a JTAG EXTEST method.
The JTAG EXTEST instruction controls the logic value that appears on each of the I/O pins 12 of the component 2. The logic values are shifted into the component 2 using the four-wire JTAG interface 4. Data must be shifted into all input/output (I/O) pin locations 12 for every new I/O vector applied. In other words, to toggle a single output pin requires writing values and shifting them into all the I/O locations, potentially requiring hundreds of JTAG clock cycles to transfer a complete set of data. To monitor logic values applied to one of the I/O pins, the data can be shifted back through the JTAG boundary scan chain.
The JTAG EXTEST method offers the advantage of a low cost alternative for programming an attached memory device, since all required logic is already part of the basic JTAG support. A disadvantage of the JTAG EXTEST method, however, is that bandwidth is limited because all I/O control bits must be written into by serially shifting in all pin data, even if only a single output needs changing, making programming relatively slow. A further disadvantage to programming using the JTAG EXTEXT method is that the programming procedure is somewhat complex. To write data to the attached memory 8, software in the host programmer 14 attached to the JTAG interface port 4 will typically need to convert the data into multiple vectors and map the vectors to the appropriate positions in the JTAG boundary scan 10. Similarly, any logic values read from I/O pins must be extracted through the JTAG boundary scan chain 10 to scan-out data.
It would be desirable to provide a method for programming an external configuration memory device that does not have a JTAG interface through the JTAG interface of a component without experiencing the disadvantages of the JTAG EXTEST method.